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6.0 Module Instances

 

 

Syntax

Port Order Connections

module_name instance_name [instance_array_range] (signal, signal, ... );

Port Name Connections

module_name instance_name [instance_array_range] (.port_name(signal), (.port_name(signal), ...);

Explicit Parameter Redefinition

defparam heirarchy_path.parameter_name = value;

Implicit Parameter Redefinition

module_name #(value) instance_name (signals);

A module may be instantiated using port order or port names.

  • Port order instantiation lists signal connections in the same order as the port list in the module definition. Unconnected ports are designated by two commas with no signal listed.
  • Port name instantiation lists the port name and signal connected to it, in any order.

instance_name (required) is used to make multiple instances of the same module unique from one another.

instance_array_range (optional) instantiates multiple modules, each instance connected to separate bits of a vector.

  • The range is specified as [lhi:rhi] (left-hand-index to right-hand-index).
  • If the bit width of a module port in the array is the same as the width of the signal connected to it, the full signal is connected to each instance of the module port.
  • If the bit width of a module port is different than the width of the signal connected to it, each module port instance is connected to a part select of the signal, with the right-most instance index connected to the right-most part of the vector, and progressing towards the left.
  • There must be the correct number of bits in each signal to connect to all instances (the signal size and port size must be multiples).

Parameters in a module may be redefined for each instance.

  • Explicit redefinition uses a defparam statement with the parameter's hierarchical name.
  • Implicit redefinition uses the # token as part of the module instantiation. Parameters must be redefined in the same order they are declared within the module.

Module Instance Examples

module reg4 (q, d, clock);
  output [3:0] q;
  input [3:0] d;
  input clock;
  wire [3:0] q, d;
  wire clock;
  
  //port order connection,2nd port not connected
  dff u1 (q[0], , d[0], clock);

  //port name connection, qb not connected
  dff u2 (.clk(clock),.q(q[1]),.data(d[1]));

  //explicit parameter redefine
  dff u3 (q[2], ,d[2], clock);
  defparam u3.delay = 3.2;

  //implicit parameter redefine
  dff #(2) u4 (q[3], , d[3], clock);
endmodule
module dff (q, qb, data, clk);
  output q, qb;
  input data, clk;

  parameter delay = 1; //default delay parameter

  dff_udp #(delay) (q, data, clk);
  not (qb, q);
endmodule
 

Array of Instances Example

module tribuf64bit (out, in, enable);
  output [63:0] out;
  input [63:0] in;
  input enable;
  wire [63:0] out, in;
  wire enable;
  
  //array of 8 8-bit tri-state buffers; each instance is connected
  //to 8-bit part selects of the 64-bit vectors; The scalar
  //enable line is connected to all instances

  tribuf8bit i[7:0] (out, in, enable);

endmodule
module tribuf8bit (out, in, enable);
  output [7:0] y;
  input [7:0] a;
  input en;
  wire [7:0] y, a;
  wire en;
  
  //array of 8 Verilog tri-state primitives each bit of the
  //vectors is connected to a different primitive instance
  bufif1 u[7:0] (y, a, en);
endmodule

 

 

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