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11.0 Synthesis Supported Constructs

 

Following is a list of Verilog HDL constructs supported by most synthesis tools.

  • This list is not specific to any one tool - each synthesis tool supports a unique subset of the Verilog language.
  • The constructs listed in this section represent a subset of the Verilog HDL that are supported by most synthesis tools.
  • Verilog constructs not listed in this section may be supported by some synthesis tools - refer to the specific synthesis tool documentation.

Verilog HDL Constructs

Notes

module declarations both module and macromodule keywords fully supported
port declarations
input output inout
fully supported; any vector size supported
net data types
wire wand wor
supply0 supply1
scalars and vectors fully supported
register data types
reg integer
register variables:
  • may be scalar or vector or register array
  • may be restricted to only making assignments to a register from just one procedure
  • integers default to 32 bits
parameter constants limited to integers; parameter redefinition may not be supported
module instances fully supported; both port order and port name instantiation supported
primitive instances
and nand or nor
xor buf not
bufif1 bufif0
notif1 notif0
only gate primitives are supported
assign
continuous assignment
fully supported; both explicit and implicit forms supported
function definitions may only use supported constructs; must be defined before being referenced
task definitions may only use supported constructs; must be defined before being referenced
always procedural block must have a sensitivity list
begin--end
statement groups
fully supported; named and unnamed blocks supported
disable statement group must be used within the same named block that is being disabled
= blocking procedural assignment
<= non-blocking procedural assignment
fully supported; may be restricted to using only one type of assignment for all assignments to the same register variable
assign procedural continuous assignment fully supported; the deassign keyword may not be supported
integer values fully supported; all sizes and bases
if if-else
case casex casez

decision statements
logic X and Z only supported as don't care bits
for loops the step assignment must be an increment or decrement (+ -)
while loops
forever loops
loop must take one clock cycle for each loop cycle (i.e.: an @(posedge clk) or @(negedge clk) must be within the loop)
operators
& ~& | ~| ^ ^~ ~^
== != < > <= =>
! && ||
<< >> {} {{}} ?:
+ - * /
operands may be:
  • scalar or vector
  • constant or variable
  • The divisor for divide operator may be restricted to constants and a power of 2
  • the === and !== operators are not supported
vector bit selects
vector part selects
fully supported on the right-hand side of an assignment; restricted to constant bit or part selects on the left-hand side of an assignment

 

 

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