10.0 User Defined Primitives


Verilog HDL constructs that represent hierarchy scope are:

Each scope has its own name space. An identifier name defined within a scope is unique to that scope. References to an identifier name will search first in the local scope, and then search upward through the scope hierarchy up to a module boundary.

UDP Table Entries
UDP Symbols 
UDP Examples





primitive primitive_name (output, input, input, ... );
  output terminal_declaration;
  input terminal_declaration;
  reg output_terminal;
  initial output_terminal = logic_value;


User Defined Primitives define new primitives, which are used exactly the same as built-in primitives.

  • All terminals must be scalar (1-bit).
  • Only one output is allowed, which must be the first terminal.
  • The maximum number of inputs is at least 9 inputs for a sequential UDP and 10 inputs for a combinational UDP.
  • Logic levels of 0, 1, X and transitions between those values may be represented in the table. The logic value Z is not supported with UDPs.
  • reg declaration (optional) defines a sequential UDP by creating internal storage. Only the output may be a reg.
  • initial (optional) is used to define the initial (power-up) state for sequential UDP's. Only the logic values 0, 1, and X may be used. The default state is X.



UDP Table Entries 

input_logic_values : output_logic_value ;

  • Combinational logic table entry. Only logic level values may be specified (0, 1, X and don't care).

input_logic_values : previous_state : output_logic_value ;

  • Sequential logic table entry. May only be used when the output is also declared as a reg data type. Both input logic level and input logic transition values may be specified.
  • A white space must separate each input value in the table.
  • The input values in the table must be listed in the same order as the terminal list in the primitive statement.
  • Any combination of input values not specified in the table will result in a logic X (unknown) value on the output.
  • Only one signal may have an edge transition specified for each entry in the table.
  • If an edge transition is specified for one input, the UDP becomes sensitive to transitions on all inputs. Therefore, all other inputs must have table entries to cover transitions, or when the transition occurs the UDP will output an X.
  • Level sensitive table entries have precedence over edge sensitive table entries.



UDP Symbols


Truth Table Symbol



logic 0 on input or output


logic 1 on input or output

x or X

unknown on input or output


no change on output (may only be used with sequential UDPs)


don't care if an input is 0, 1, or X

b or B

don't care if and input is 0 or 1


input transition from logic v to logic w
e.g.: (01) represents transition from 0 to 1

r or R

rising input transition: same as (01)

f or F

falling input transition: same as (10)

p or P

positive input transition: (01), (0X) or (X1)

n or N

negative input transition: (10), (1X) or (X0)


any possible input transition: same as (??)




UDP Examples


UDP Examples

primitive mux (y, a, b, sel); //COMBINATIONAL UDP
  output y;
  input sel, a, b;
  table  //table order for inputs matches primitive statement
  // a  b  sel : y
     0  ?   0  : 0;  //select a; don't care about b
     1  ?   0  : 1;  //select a; don't care about b
     ?  0   1  : 0;  //select b; don't care about a
     ?  1   1  : 1;  //select b; don't care about a
primitive dff (q,d,clk,rst); //SEQUENTIAL UDP
  output q;
  input clk, rst, d;
  reg q; //declaring output as reg defines
         //sequential device with an internal
         //storage state
  initial q = 0; //powers up in reset state
  // d  clk rst:state:q
     ?   ?   0 :  ?  :0; //low true reset
     0   R   1 :  ?  :0; //clock in a 0
     1   R   1 :  ?  :1: //clock in a 1
     ?   N   1 :  ?  :-; //ignore negedge of clk
     *   ?   1 :  ?  :-; //ignore all edges on d
     ?   ?   P :  ?  :-; //ignore posedge of rst
     0 (0X)  1 :  0  :-; //reduce pessimism
     1 (0X)  1 :  1  :-; //reduce pessimism